A memory cell with one transistor has already been described by the present inventors in unpublished French patent application 10/52612 of Jul. 4, 2010 (B10224).
FIG. 1 is a copy of FIG. 1 of this French patent application. The memory cell comprises a MOS transistor formed on an insulating layer 1 resting on a support 3, generally, a silicon plate. The area occupied by the MOS transistor, or active area, is delimited by an insulating periphery 5. The MOS transistor comprises heavily-doped source and drain regions of a first conductivity type 7 and 8 separated by a bulk region. The source and drain regions respectively form one piece with a source metallization 10 and a drain metallization 11 connected to source and drain terminals S and D. The bulk portion of the transistor is topped with an insulated gate 12 connected to a gate terminal G. The bulk region is divided widthwise into an upper bulk region 13 on the side of gate 12 and a lower bulk region 14 in the vicinity of insulating layer 1. Upper bulk region 13 is of the conductivity type opposite to that of the drain/source and preferably has a doping level lower than 1016 atoms/cm3. Lower bulk region 14 is of the same conductivity type as the drain/source. Its doping level is preferably selected to be in a range from 1016 to 1018 atoms/cm3 according to its thickness so that lower portion 14 is fully depleted at state 0 and that it contains a sufficient quantity of available electrons at state 1, states 0 and 1 being defined hereafter.
This French patent application also describes a write and read mode for this memory cell.
To write a 1, a relatively high positive voltage, for example, from 1 to 3 volts, is first applied to the transistor drain, and the gate is set to a positive potential for a short time, while the positive voltage is applied to the drain. As a result, a channel region is formed in the upper bulk region (during this phase, a low proportion of current may without any disadvantage flow through the lower bulk region) while electrons flow from the source to the drain. Given that the drain-source potential difference is selected to be relatively high, these electrons will create by impact electron-hole pairs in the upper bulk region. The created electrons take part in the current flow, and the holes remain in the upper bulk region. If the current flow between source and drain is abruptly interrupted, by switching the gate to a negative potential before switching the drain, holes will remain in upper bulk region 13.
To write a 0 into the memory cell, the gate is made positive again but this time, drain 8 is connected to a slightly positive, zero, or even negative voltage. Then, the source-drain potential difference is insufficient for the creation of electron-hole pairs and, due to the electrostatic biasing created by the gate in upper bulk region 13, the holes that may be present in this upper bulk region will be drained off to the drain and/or to the source. Thus, in one case (writing of a 1), holes are stored in upper bulk region 13 and in the other case (writing of a 0), no charge is stored in this upper bulk region.
In read phase, a negative voltage is applied to the gate and a slightly positive voltage is applied to the drain. In hold phase, a negative voltage is applied to the gate and a zero voltage is applied to the drain.
In the case where a 0 has been stored, that is, no charge is stored in upper bulk region 13, the transistors in parallel sharing a same drain and a same source are both blocked: no current flows through the transistor corresponding to the upper bulk region since the gate is negative, and the negative gate voltage depletes the lower bulk region which thus also lets no current flow. It should be understood that the upper bulk region should be sufficiently thin for the gate to have a sufficient influence on the lower bulk region, whereby it has been indicated that the upper bulk region has a thickness preferably close to 10 nm.
However, in the case where a 1 has been written, that is, positive charges are stored in upper bulk region 13, no current flows through the transistor corresponding to this upper bulk region since the gate is negative and no electric channel region is created in the upper bulk region. However, the positive charges stored in the upper bulk region shield the negative gate potential and an electron current will flow through the transistor having, as a source and drain, regions 7 and 8 and, as a bulk, non-depleted lower bulk region 14.
Thus, a state 1 may be recognized from a state 0 by the flowing of a current or the fact that no current flows during a read phase.
It should also be noted that due to the fact that during the read state, only a slightly positive potential is applied to the drain, no charges are created by impact in lower bulk region 14 during a reading.
FIG. 7 of this patent application is copied in FIG. 2 of the present application. This drawing very schematically illustrates a FINFET embodiment of a variation of the structure of FIG. 1. The transistor bulk, instead of being divided in two regions, is divided in three regions: a left-hand P-type region 41, a central N-type region 43, and a right-hand P-type region 45. An insulated gate 46 is arranged in front of left-hand region 41 and an insulated gate 47 is arranged in front of right-hand region 45. A two-bit memory cell, that is, a four-state memory cell, is thus obtained. The left-hand gate enables to store or not charges in left-hand bulk region 41. The right-hand gate enables to store or not charges in right-hand bulk region 45. A first state (11) is obtained if charges are stored on the left-hand side and on the right-hand side, a second state (00) is obtained if no charge is stored, either on the left-hand side or on the right-hand side, a third state (10) is obtained if charges are stored on the left-band side and not on the right-hand side, and a fourth state (01) is obtained if charges are stored in the right-hand region and not on the left-hand side. States (01) and (10) can be differentiated in various ways. Particularly, if the left-hand and right-hand gates are different (different work function or different insulator thickness) and/or if the applied voltages are different, a variable quantity of charges will be stored in the left-hand bulk region and in the right-hand bulk region on each writing of a 1. Thus, the four possible values of the current in the central bulk region can be well differentiated.
It should be noted that in the embodiment illustrated in FIG. 2, the two gates are distinct and controlled independently to determine different states of the memory cell.